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NCP5005
V bat
U1
V bat
C1
4
EN
V bat
5
L1
4.7 m F
22 m H
PWM
Average Network
R2
R3
GND
2
3
GND
FB
V out 1
D1
MBR0530
GND
150 k
10 k
C3
100 nF
R4
5.6 k
NCP5005
C2
1.0 m F
GND
GND
R1
D6
D5
D4
D3
D2
GND
NOTE: RC filter R2 and C3 is optional (see text)
10 W
LWT67C LWT67C LWT67C LWT67C LWT67C
Sense Resistor
Figure 29. Basic DC Current Mode Operation with PWM Control
To implement such a function, let consider the feedback
input as an operational amplifier with a high impedance
input (reference schematic Figure 29). The analog loop
will keep going to balance the current flowing through the
sense resistor R1 until the feedback voltage is 200 mV. An
extra resistor (R4) isolates the FB node from low resistance
to ground, making possible to add an external voltage to
this pin.
The time constant R2/C3 generates the voltage across C3,
added to the node Pin 1, while R2/R3/R4/R1/C3 create the
discharge time constant. In order to minimize the pick up
value, preferably well below 1.0 M W . Consequently, let R2 =
150 k, R3 = 10 k and R4 = 5.6 k. On the other hand, the
feedback delay to control the luminosity of the LED shall be
acceptable by the user, 10 ms or less being a good
compromise. The time constant can now be calculated based
on a 400 mV offset voltage at the C3/R2/R3 node to force
zero current to the LED. Assuming the PWM signal comes
from a standard gate powered by a 3.0 V supply, running at
10 kHz, then a full dimming of the LED can be achieved with
a 95% span of the Duty Cycle signal. Figure 30 depicts the
behavior under such PWM analog mode.
noise at FB node, the resistors shall have relative medium
PWM
VFB
VPWM
Figure 30. Operation with Analog PWM, f = 10 kHz, DC = 25%
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